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FEATURES
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LTC3729 550kHz, PolyPhase, High Efficiency, Synchronous Step-Down Switching Regulator DESCRIPTIO
The LTC(R)3729 is a multiple phase, synchronous stepdown current mode switching regulator controller that drives N-channel external power MOSFET stages in a phase-lockable fixed frequency architecture. The PolyPhase controller drives its two output stages out of phase at frequencies up to 550kHz to minimize the RMS ripple currents in both input and output capacitors. The output clock signal allows expansion for up to 12 evenly phased controllers for systems requiring 15A to 200A of output current. The multiple phase technique effectively multiplies the fundamental frequency by the number of channels used, improving transient response while operating each channel at an optimum frequency for efficiency. Thermal design is also simplified. An internal differential amplifier provides true remote sensing of the regulated supply's positive and negative output terminals as required for high current applications. A RUN/SS pin provides both soft-start and optional timed, short-circuit shutdown. Current foldback limits MOSFET dissipation during short-circuit conditions when the overcurrent latchoff is disabled. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The LTC3729 includes a power good output pin that indicates when the output is within 7.5% of the designed set point.
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Wide VIN Range: 4V to 36V Operation Reduces Required Input Capacitance and Power Supply Induced Noise 1% Output Voltage Accuracy Phase-Lockable Fixed Frequency: 250kHz to 550kHz True Remote Sensing Differential Amplifier PolyPhaseTM Extends from Two to Twelve Phases Reduces the Size and Value of Inductors Current Mode Control Ensures Current Sharing 1.1MHz Effective Switching Frequency (2-Phase) OPTI-LOOP(R) Compensation Reduces COUT Power Good Output Voltage Indicator Very Low Dropout Operation: 99% Duty Cycle Adjustable Soft-Start Current Ramping Internal Current Foldback Plus Shutdown Timer Overvoltage Soft-Latch Eliminates Nuisance Trips Available in 5mm x 5mm QFN and 28-Lead SSOP Packages
APPLICATIO S
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Desktop Computers/Servers Large Memory Arrays DC Power Distribution Systems
, LTC and LT are registered trademarks of Linear Technology Corporation. OPTI-LOOP is a registered trademark of Linear Technology Corporation. PolyPhase is a trademark of Linear Technology Corporation.
TYPICAL APPLICATIO
0.1F
S
VIN
LTC3729
10 TG1 SW1
S
M1 0.47F
S
0.1F RUN/SS PGOOD ITH 3.3k
S
BOOST1 BG1 PGND SENSE1 + SENSE1 - TG2 SGND BOOST2 SW2 VDIFFOUT BG2 EAIN VOS
-
S
0.002 M2 x2 L1 D1 0.8H
1000pF
M3
S
0.47F
S
0.002 M4 x2 L2 0.8H
16k
S
D2
+
INTVCC SENSE2 + SENSE2 -
S
10F
16k
VOS +
COUT: T510E108K004AS D1, D2: UP5840
L1, L2: CEPH149-IROMC
M1, M3: IRF7811W M2, M4: IRF7822
Figure 1. High Current Dual Phase Step-Down Converter
U
U
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10F 35V CERAMIC x4
VIN 5V TO 28V
VOUT 1.6V/40A
+
COUT 1000F x2 4V
3729 TA01
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LTC3729
ABSOLUTE
AXI U RATI GS
Input Supply Voltage (VIN).........................36V to - 0.3V Topside Driver Voltages (BOOST1,2) .........42V to - 0.3V Switch Voltage (SW1, 2) .............................36V to - 5 V SENSE1+, SENSE2 +, SENSE1-, SENSE2 - Voltages ........................ (1.1)INTVCC to - 0.3V EAIN, VOS+, VOS-, EXTVCC, INTVCC, RUN/SS, PGOOD Voltages ...........................7V to - 0.3V Boosted Driver Voltage (BOOST-SW) ..........7V to - 0.3V PLLFLTR, PLLIN, CLKOUT, PHASMD, VDIFFOUT Voltages ................................ INTVCC to - 0.3V
PACKAGE/ORDER I FOR ATIO
TOP VIEW RUN/SS SENSE1 + SENSE1 - EAIN PLLFLTR PLLIN PHASMD ITH SGND 1 2 3 4 5 6 7 8 9 28 CLKOUT 27 TG1 26 SW1 25 BOOST1 24 VIN 23 BG1 22 EXTVCC 21 INTVCC 20 PGND 19 BG2 18 BOOST2 17 SW2 16 TG2 15 PGOOD
SENSE1-
SENSE1+
CLKOUT
RUN/SS
ORDER PART NUMBER
NC
SW1
TG1
NC
LTC3729EG
EAIN 1 PLLFLTR 2 PLLIN 3 PHASMD 4 ITH 5 SGND 6 VDIFFOUT 7 VOS- 8
VDIFFOUT 10 VOS - 11 VOS + SENSE2
-
SENSE2+
PGOOD
-
TG2
SW2
NC
13
SENSE2 + 14
G PACKAGE 28-LEAD PLASTIC SSOP TJMAX = 125C, JA = 95C/W
UH PACKAGE 32-LEAD 5mm x 5mm PLASTIC QFN
JA = 34C/W EXPOSED PAD IS SGND (MUST BE SOLDERED TO PCB)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL VEAIN VSENSEMAX IINEAIN VLOADREG PARAMETER Regulated Feedback Voltage Maximum Current Sense Threshold Feedback Current Output Voltage Load Regulation Main Control Loop
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 15V, VRUN/SS = 5V unless otherwise noted.
CONDITIONS (Note 3); ITH Voltage = 1.2V VSENSE VSENSE1, 2 = 5V (Note 3) (Note 3) Measured in Servo Loop; ITH Voltage = 0.7V Measured in Servo Loop; ITH Voltage = 2V
q q
- = 5V
SENSE2
12
VOS+
NC
2
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W
WW U
W
(Note 1)
ITH Voltage ................................................2.7V to - 0.3V Peak Output Current <1s(TGL1,2, BG1,2) ................ 5A INTVCC RMS Output Current ................................ 50mA Operating Ambient Temperature Range (Note 6) ................................... - 40C to 85C Junction Temperature (Note 2) ............................. 125C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec) (G Package Only) .................................................. 300C
TOP VIEW
ORDER PART NUMBER LTC3729EUH
24 BOOST1 23 VIN 22 BG1 21 EXTVCC 20 INTVCC 19 PGND 18 BG2 17 BOOST2
32 31 30 29 28 27 26 25
UH PART MARKING 3729
9 10 11 12 13 14 15 16
MIN
q q
TYP 0.800 75 75 -5 0.1 - 0.1
MAX 0.808 88 85 - 50 0.5 - 0.5
UNITS V mV mV nA % %
0.792 62 65
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LTC3729
ELECTRICAL CHARACTERISTICS
SYMBOL VREFLNREG VOVL UVLO gm gmOL IQ PARAMETER Reference Voltage Line Regulation Output Overvoltage Threshold Undervoltage Lockout Transconductance Amplifier gm Transconductance Amplifier Gain Input DC Supply Current Normal Mode Shutdown Soft-Start Charge Current RUN/SS Pin ON Threshold RUN/SS Pin Latchoff Arming RUN/SS Discharge Current Shutdown Latch Disable Current Total Sense Pins Source Current Maximum Duty Factor Top Gate Transition Time: Rise Time Fall Time Bottom Gate Transition Time: Rise Time Fall Time Top Gate Off to Bottom Gate On Delay Synchronous Switch-On Delay Time Bottom Gate Off to Top Gate On Delay Top Switch-On Delay Time Minimum On-Time Internal VCC Voltage INTVCC Load Regulation EXTVCC Voltage Drop EXTVCC Switchover Voltage EXTVCC Switchover Hysteresis Nominal Frequency Lowest Frequency Highest Frequency PLLIN Input Resistance Phase Detector Output Current Sinking Capability Sourcing Capability Controller 2-Controller 1 Phase fPLLIN < fOSC fPLLIN > fOSC VPHASMD = 0V, Open VPHASMD = 5V
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 15V, VRUN/SS = 5V unless otherwise noted.
CONDITIONS VIN = 3.6V to 30V (Note 3) Measured at VEAIN VIN Ramping Down ITH = 1.2V; Sink/Source 5A; (Note 3) ITH = 1.2V; (gmxZL; No Ext Load); (Note 3) (Note 4) EXTVCC Tied to VOUT; VOUT = 5V VRUN/SS = 0V VRUN/SS = 1.9V VRUN/SS Rising VRUN/SS Rising from 3V Soft Short Condition VEAIN = 0.5V; VRUN/SS = 4.5V VEAIN = 0.5V Each Channel; VSENSE1 -, 2 - = VSENSE1+, 2 + = 0V In Dropout CLOAD = 3300pF CLOAD = 3300pF CLOAD = 3300pF CLOAD = 3300pF CLOAD = 3300pF Each Driver CLOAD = 3300pF Each Driver Tested with a Square Wave (Note 5) 6V < VIN < 30V; VEXTVCC = 4V ICC = 0 to 20mA; VEXTVCC = 4V ICC = 20mA; VEXTVCC = 5V ICC = 20mA, EXTVCC Ramping Positive ICC = 20mA, EXTVCC Ramping Negative VPLLFLTR = 1.2V VPLLFLTR = 0V VPLLFLTR 2.4V 360 230 480
q q
MIN 0.84 3
TYP 0.002 0.86 3.5 3 1.5 580 20
MAX 0.02 0.88 4
UNITS %/V V V mmho V/mV A A A V V A A A %
40 1.9 4.5 4 5
IRUN/SS VRUN/SS VRUN/SSLO ISCL ISDLDO ISENSE DFMAX TG1, 2 tr TG1, 2 tf BG1, 2 tr BG1, 2 tf TG/BG t1D BG/TG t2D tON(MIN) VINTVCC VLDO INT VLDO EXT VEXTVCC VLDOHYS fNOM fLOW fHIGH RPLLIN IPLLFLTR
- 0.5 1.0 0.5 - 85 98
- 1.2 1.5 3.8 2 1.6 - 60 99.5 30 40 30 20 90 90 100 90 90 90 90
ns ns ns ns ns ns ns
Internal VCC Regulator 4.8 5.0 0.2 80 4.5 4.7 0.2 400 260 550 50 - 15 15 180 240 440 290 590 5.2 1.0 160 V % mV V V kHz kHz kHz k A A Deg Deg
Oscillator and Phase-Locked Loop
RRELPHS
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LTC3729
ELECTRICAL CHARACTERISTICS
SYMBOL CLKOUT PARAMETER Phase (Relative to Controller 1)
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 15V, VRUN/SS = 5V unless otherwise noted.
CONDITIONS VPHASMD = 0V VPHASMD = Open VPHASMD = 5V 4 0.2 IPGOOD = 2mA VPGOOD = 5V VEAIN with Respect to Set Output Voltage VEAIN Ramping Negative VEAIN Ramping Positive -6 6 0.995 0V < VCM < 5V Measured at VOS + Input 46 - 7.5 7.5 1 55 80 0.1 0.3 1 - 9.5 9.5 1.005 MIN TYP 60 90 120 MAX UNITS Deg Deg Deg V V V A % % V/V dB k
CLKHIGH CLKLOW VPGL IPGOOD VPG
Clock High Output Voltage Clock Low Output Voltage PGOOD Voltage Low PGOOD Leakage Current PGOOD Trip Level, Either Controller
PGOOD Output
Differential Amplifier ADA CMRRDA RIN Gain Common Mode Rejection Ratio Input Resistance
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LTC3729EG: TJ = TA + (PD * 95C/W) LTC3729EUH: TJ = TA + (PD * 34C/W) Note 3: The LTC3729 is tested in a feedback loop that servos VITH to a specified voltage and measures the resultant VEAIN.
Note 4: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 5: The minimum on-time condition corresponds to the on inductor peak-to-peak ripple current 40% of IMAX (see Minimum On-Time Considerations in the Applications Information section). Note 6: The LTC3729E is guaranteed to meet performance specifications from 0C to 70C. Specifications over the - 40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls.
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Output Current (Figure 12)
100 100 VEXTVCC = 5V 80 VIN = 5V
EFFICIENCY (%) EFFICIENCY (%)
60
VIN = 12V VIN = 20V
80
40 VOUT = 3.3V VEXTVCC = 5V IOUT = 20A f = 250kHz 0.1 1 10 OUTPUT CURRENT (A) 100
3729 G01
70
EFFICIENCY (%)
VIN = 8V
20
0
4
UW
Efficiency vs Output Current (Figure 12)
100
Efficiency vs Input Voltage (Figure 12)
VOUT = 3.3V VEXTVCC = 5V IOUT = 20A f = 250kHz 90
90 VEXTVCC = 0V
80
60 VOUT = 3.3V f = 250kHz 1 10 OUTPUT CURRENT (A) 100
3729 G02
50
70 5 10 VIN (V)
3729 G03
15
20
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LTC3729 TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Input Voltage and Mode
1000 250
INTVCC AND EXTVCC SWITCH VOLTAGE (V)
EXTVCC VOLTAGE DROP (mV)
800
SUPPLY CURRENT (A)
600 ON 400
200 SHUTDOWN 0 0 5 20 15 10 25 INPUT VOLTAGE (V) 30 35
Internal 5V LDO Line Reg
5.1 5.0
ILOAD = 1mA
INTVCC VOLTAGE (V)
4.9
VSENSE (mV)
4.8 4.7 4.6 4.5 4.4 0 5 20 15 25 10 INPUT VOLTAGE (V) 30 35
3729 G07
VSENSE (mV)
Maximum Current Sense Threshold vs VRUN/SS (Soft-Start)
80 VSENSE(CM) = 1.6V
80
60
VSENSE (mV)
VSENSE (mV)
72
VSENSE (mV)
40
20
64
0 0 1 2 3 VRUN/SS (V)
3729 G10
4
UW
3729 G04
EXTVCC Voltage Drop
5.05 5.00 4.95 4.90 4.85 4.80 4.75
INTVCC and EXTVCC Switch Voltage vs Temperature
INTVCC VOLTAGE
200
150
100
50
EXTVCC SWITCHOVER THRESHOLD
0
0
10
30 20 CURRENT (mA)
40
50
3729 G05
4.70 - 50 - 25
50 25 75 0 TEMPERATURE (C)
100
125
3729 G06
Maximum Current Sense Threshold vs Duty Factor
75
80 70 60
Maximum Current Sense Threshold vs Percent of Nominal Output Voltage (Foldback)
50
50 40 30 20 10
25
0 0 20 40 60 DUTY FACTOR (%) 80 100
3729 G08
0
50 100 0 25 75 PERCENT ON NOMINAL OUTPUT VOLTAGE (%)
3729 G09
Maximum Current Sense Threshold vs Sense Common Mode Voltage
90 80 76 70 60 50 40 30 20 10 0 -10 -20 60 -30
Current Sense Threshold vs ITH Voltage
68
5
6
0
1 3 4 2 COMMON MODE VOLTAGE (V)
5
3729 G11
0
0.5
1
1.5 VITH (V)
2
2.5
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LTC3729 TYPICAL PERFOR A CE CHARACTERISTICS
Load Regulation
0.0 FCB = 0V VIN = 15V FIGURE 1
2.5
NORMALIZED VOUT (%)
-0.1
-0.2
VITH (V)
1.5
ISENSE (A)
-0.3
0.5
-0.4
0
1
3 2 LOAD CURRENT (A)
Maximum Current Sense Threshold vs Temperature
80 1.8 1.6 78
RUN/SS CURRENT (A)
VSENSE (mV)
76
74
72
70 -50
-25
Soft-Start Up (Figure 12)
VITH 1V/DIV IOUT O/30A VITH 1V/DIV VOUT 200mV/DIV
VOUT 2V/DIV VRUNSS 2V/DIV
6
UW
4 5
3729 G13
VITH vs VRUN/SS
VOSENSE = 0.7V
SENSE Pins Total Source Current
100
2.0
50
0
1.0
-50
0
0
1
2
3 VRUN/SS (V)
4
5
6
3729 G14
-100
0
2
4
6
3729 G15
VSENSE COMMON MODE VOLTAGE (V)
RUN/SS Current vs Temperature
1.4 1.2 1.0 0.8 0.6 0.4 0.2
50 25 0 75 TEMPERATURE (C)
100
125
0 -50
-25
0 25 50 75 TEMPERATURE (C)
100
125
3729 G17
3729 G19
Load Step (Figure 12)
100ms/DIV
3729 G20
10s/DIV
3729 G21
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LTC3729 TYPICAL PERFOR A CE CHARACTERISTICS
Current Sense Pin Input Current vs Temperature
35
CURRENT SENSE INPUT CURRENT (A)
VOUT = 5V
EXTVCC SWITCH RESISTANCE ()
33
FREQUENCY (kHz)
31
29
27
25 -50 -25
50 25 0 75 TEMPERATURE (C)
Undervoltage Lockout vs Temperature
3.50 3.45 3.40 3.35 3.30 3.25 3.20 -50 -25 4.5
SHUTDOWN LATCH THRESHOLDS (V)
UNDERVOLTAGE LOCKOUT (V)
50 25 75 0 TEMPERATURE (C)
PI FU CTIO S
G Package/UH Package
RUN/SS (Pin 1/Pin 28): Combination of Soft-Start, Run Control Input and Short-Circuit Detection Timer. A capacitor to ground at this pin sets the ramp time to full current output. Forcing this pin below 0.8V causes the IC to shut down all internal circuitry. All functions are disabled in shutdown. SENSE1+, SENSE2+ (Pins 2,14/Pins 30, 12): The (+) Input to the Differential Current Comparators. The ITH pin voltage and built-in offsets between SENSE- and SENSE+
UW
100 125
3729 G23
EXTVCC Switch Resistance vs Temperature
10 700 600 8 500 400 300 200 100 0 -50 -25
Oscillator Frequency vs Temperature
VPLLFLTR = 2.4V
6
VPLLFLTR = 1.2V
4
VPLLFLTR = 0V
2
50 25 0 75 TEMPERATURE (C)
100
125
0 - 50 - 25
50 25 75 0 TEMPERATURE (C)
100
125
3729 G24
3729 G25
Shutdown Latch Thresholds vs Temperature
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 LATCHOFF THRESHOLD LATCH ARMING
100
125
3729 G26
3729 G27
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pins in conjunction with RSENSE set the current trip threshold. SENSE1-, SENSE2- (Pins 3, 13/Pins 31, 11): The (-) Input to the Differential Current Comparators. EAIN (Pin 4/Pin 1): Input to the Error Amplifier that compares the feedback voltage to the internal 0.8V reference voltage. This pin is normally connected to a resistive divider from the output of the differential amplifier (DIFFOUT).
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LTC3729
PI FU CTIO S G Package/UH Package
PLLFLTR (Pin 5/Pin 2): The Phase-Locked Loop's Low Pass Filter is tied to this pin. Alternatively, this pin can be driven with an AC or DC voltage source to vary the frequency of the internal oscillator. PLLIN (Pin 6/Pin 3): External Synchronization Input to Phase Detector. This pin is internally terminated to SGND with 50k. The phase-locked loop will force the rising top gate signal of controller 1 to be synchronized with the rising edge of the PLLIN signal. PHASMD (Pin 7/Pin 4): Control Input to Phase Selector which determines the phase relationships between controller 1, controller 2 and the CLKOUT signal. ITH (Pin 8/Pin 5): Error Amplifier Output and Switching Regulator Compensation Point. Both current comparator's thresholds increase with this control voltage. The normal voltage range of this pin is from 0V to 2.4V. SGND (Pin 9/Pin 6): Signal Ground, common to both controllers, must be routed separately from the input switched current ground path to the common (-) terminal(s) of the COUT capacitor(s). VDIFFOUT (Pin 10/Pin 7): Output of a Differential Amplifier that provides true remote output voltage sensing. This pin normally drives an external resistive divider that sets the output voltage. VOS-, VOS+ (Pins 11, 12/Pins 8, 9): Inputs to an Operational Amplifier. Internal precision resistors capable of being electronically switched in or out can configure it as a differential amplifier or an uncommitted Op Amp. PGOOD (Pin 15/Pin 13): Open-Drain Logic Output. PGOOD is pulled to ground when the voltage on the EAIN pin is not within 7.5% of its set point. TG2, TG1 (Pins 16, 27/Pins 14, 26): High Current Gate Drives for Top N-Channel MOSFETS. These are the outputs of floating drivers with a voltage swing equal to INTVCC superimposed on the switch node voltage SW. SW2, SW1 (Pins 17, 26/Pins 15, 25): Switch Node Connections to Inductors. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to VIN. BOOST2, BOOST1 (Pins 18, 25/Pins 17, 24): Bootstrapped Supplies to the Topside Floating Drivers. Capacitors are connected between the Boost and Switch pins and Schottky diodes are tied between the Boost and INTV CC pins. Voltage swing at the Boost pins is from INTV CC to (VIN + INTVCC). BG2, BG1 (Pins 19, 23/Pins 18, 22): High Current Gate Drives for Bottom Synchronous N-Channel MOSFETS. Voltage swing at these pins is from ground to INTVCC. PGND (Pin 20/Pin 19): Driver Power Ground. Connect to sources of bottom N-channel MOSFETS and the (-) terminals of CIN. INTVCC (Pin 21/Pin 20): Output of the Internal 5V Linear Low Dropout Regulator and the EXTVCC Switch. The driver and control circuits are powered from this voltage source. Decouple to power ground with a 1F ceramic capacitor placed directly adjacent to the IC and minimum of 4.7F additional tantalum or other low ESR capacitor. EXTVCC (Pin 22/Pin 21): External Power Input to an Internal Switch . This switch closes and supplies INTVCC, bypassing the internal low dropout regulator whenever EXTVCC is higher than 4.7V. See EXTVCC Connection in the Applications Information section. Do not exceed 7V on this pin and ensure VEXTVCC VINTVCC. VIN (Pin 24/Pin 23): Main Supply Pin. Should be closely decoupled to the IC's signal ground pin. CLKOUT (Pin 28/Pin 27): Output Clock Signal available to daisychain other controller ICs for additional MOSFET driver stages/phases.
8
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LTC3729
FU CTIO AL DIAGRA W
INTVCC DUPLICATE FOR SECOND CONTROLLER CHANNEL BOOST DB VIN DROP OUT DET S PHASMD 2A DIFFOUT 40k 40k SHDN A1 VOS + 40k - + 40k 0.86V 4(VFB) SLOPE COMP 45k 45k 2.4V 0.74V VREF OV 4.7V EXTVCC + - 5V LDO REG - EA + + - 1.2A
SHDN RST 4(VFB)
PLLIN FIN 50k PLLLPF RLP CLKOUT CLP OSCILLATOR CLK1 CLK2 Q Q TOP BOT FCB SW SWITCH LOGIC BOT INTVCC BG PGND TG CB PHASE DET
VOS -
PGOOD
+ EAIN - + 0.80V
VOUT
EAIN R1
VIN VIN
0.80V
R2
0.86V
ITH
CC
+
5V
INTVCC 6V SGND INTERNAL SUPPLY
RUN SOFT START RUN/SS
RC
CSS
+
U
U
+
CIN
FORCE BOT
R PHASE LOGIC
INTVCC I1 - +
+ 30k SENSE
L
-
+
-
0.86V
30k
SENSE -
RSENSE
COUT
3729 FBD
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LTC3729
OPERATIO
Main Control Loop The LTC3729 uses a constant frequency, current mode step-down architecture. During normal operation, the top MOSFET is turned on each cycle when the oscillator sets the RS latch, and turned off when the main current comparator, I1, resets the RS latch. The peak inductor current at which I1 resets the RS latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier EA. The differential amplifier, A1, produces a signal equal to the differential voltage sensed across the output capacitor but re-references it to the internal signal ground (SGND) reference. The EAIN pin receives a portion of this voltage feedback signal at the DIFFOUT pin which is compared to the internal reference voltage by the EA. When the load current increases, it causes a slight decrease in the EAIN pin voltage relative to the 0.8V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on for the rest of the period. The top MOSFET drivers are biased from floating bootstrap capacitor CB, which normally is recharged during each off cycle through an external Schottky diode. When VIN decreases to a voltage close to VOUT, however, the loop may enter dropout and attempt to turn on the top MOSFET continuously. A dropout detector detects this condition and forces the top MOSFET to turn off for about 400ns every 10th cycle to recharge the bootstrap capacitor. The main control loop is shut down by pulling Pin 1 (RUN/ SS) low. Releasing RUN/SS allows an internal 1.2A current source to charge soft-start capacitor CSS. When CSS reaches 1.5V, the main control loop is enabled with the ITH voltage clamped at approximately 30% of its maximum value. As CSS continues to charge, ITH is gradually released allowing normal operation to resume. When the RUN/SS pin is low, all LTC3729 functions are shut down. If VOUT has not reached 70% of its nominal value when CSS has charged to 4.1V, an overcurrent latchoff can be invoked as described in the Applications Information section.
10
U
(Refer to Functional Diagram)
Low Current Operation The LTC3729 operates in a continuous, PWM control mode. The resulting operation at low output currents optimizes transient response at the expense of substantial negative inductor current during the latter part of the period. The level of ripple current is determined by the inductor value, input voltage, output voltage, and frequency of operation. Frequency Synchronization The phase-locked loop allows the internal oscillator to be synchronized to an external source via the PLLIN pin. The output of the phase detector at the PLLFLTR pin is also the DC frequency control input of the oscillator that operates over a 250kHz to 550kHz range corresponding to a DC voltage input from 0V to 2.4V. When locked, the PLL aligns the turn on of the top MOSFET to the rising edge of the synchronizing signal. When PLLIN is left open, the PLLFLTR pin goes low, forcing the oscillator to minimum frequency. The internal master oscillator runs at a frequency twelve times that of each controller's frequency. The PHASMD pin determines the relative phases between the internal controllers as well as the CLKOUT signal as shown in Table 1. The phases tabulated are relative to zero phase being defined as the rising edge of the top gate (TG1) driver output of controller 1.
Table 1.
VPHASMD Controller 2 CLKOUT GND 180 60 OPEN 180 90 INTVCC 240 120
The CLKOUT signal can be used to synchronize additional power stages in a multiphase power supply solution feeding a single, high current output or separate outputs. Input capacitance ESR requirements and efficiency losses are substantially reduced because the peak current drawn from the input capacitor is effectively divided by the number of phases used and power loss is proportional to the RMS current squared. A two stage, single output voltage implementation can reduce input path power loss by 75% and radically reduce the required RMS current rating of the input capacitor(s).
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LTC3729
OPERATIO
INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most of the IC circuitry is derived from INTVCC. When the EXTVCC pin is left open, an internal 5V low dropout regulator supplies INTVCC power. If the EXTVCC pin is taken above 4.7V, the 5V regulator is turned off and an internal switch is turned on connecting EXTVCC to INTVCC. This allows the INTVCC power to be derived from a high efficiency external source such as the output of the regulator itself or a secondary winding, as described in the Applications Information section. An external Schottky diode can be used to minimize the voltage drop from EXTVCC to INTVCC in applications requiring greater than the specified INTVCC current. Voltages up to 7V can be applied to EXTVCC for additional gate drive capability. Differential Amplifier This amplifier provides true differential output voltage sensing. Sensing both VOUT + and VOUT - benefits regulation in high current applications and/or applications having electrical interconnection losses. Power Good (PGOOD) The PGOOD pin is connected to the drain of an internal MOSFET. The MOSFET turns on when the output is not within 7.5% of its nominal output level as determined by
APPLICATIO S I FOR ATIO
The basic LTC3729 application circuit is shown in Figure 1 on the first page. External component selection is driven by the load requirement, and begins with the selection of RSENSE1, 2. Once RSENSE1, 2 are known, L1 and L2 can be chosen. Next, the power MOSFETs and D1 and D2 are selected. The operating frequency and the inductor are chosen based mainly on the amount of ripple current. Finally, CIN is selected for its ability to handle the input ripple current (that PolyPhase operation minimizes) and COUT is chosen with low enough ESR to meet the output ripple voltage and load step specifications (also minimized with PolyPhase). The circuit shown in Figure 1 can be configured for operation up to an input voltage of 28V (limited by the external MOSFETs).
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(Refer to Functional Diagram)
the feedback divider. When the output is within 7.5% of its nominal value, the MOSFET is turned off within 10s and the PGOOD pin should be pulled up by an external resistor to a source of up to 7V. Short-Circuit Detection The RUN/SS capacitor is used initially to limit the inrush current from the input power source. Once the controllers have been given time, as determined by the capacitor on the RUN/SS pin, to charge up the output capacitors and provide full load current, the RUN/SS capacitor is then used as a short-circuit timeout circuit. If the output voltage falls to less than 70% of its nominal output voltage the RUN/SS capacitor begins discharging assuming that the output is in a severe overcurrent and/or short-circuit condition. If the condition lasts for a long enough period as determined by the size of the RUN/SS capacitor, the controller will be shut down until the RUN/SS pin voltage is recycled. This built-in latchoff can be overidden by providing a >5A pull-up current at a compliance of 5V to the RUN/SS pin. This current shortens the soft-start period but also prevents net discharge of the RUN/SS capacitor during a severe overcurrent and/or short-circuit condition. Foldback current limiting is activated when the output voltage falls below 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled.
RSENSE Selection For Output Current RSENSE1, 2 are chosen based on the required output current. The LTC3729 current comparator has a maximum threshold of 75mV/RSENSE and an input common mode range of SGND to 1.1( INTVCC). The current comparator threshold sets the peak inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peak-to-peak ripple current, IL. Allowing a margin for variations in the LTC3729 and external component values yields: RSENSE = (50mV/IMAX)N where N = number of stages.
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When using the controller in very low dropout conditions, the maximum output current level will be reduced due to internal slope compensation required to meet stability criterion for buck regulators operating at greater than 50% duty factor. A curve is provided to estimate this reduction in peak output current level depending upon the operating duty factor. Operating Frequency The LTC3729 uses a constant frequency, phase-lockable architecture with the frequency determined by an internal capacitor. This capacitor is charged by a fixed current plus an additional current which is proportional to the voltage applied to the PLLFLTR pin. Refer to Phase-Locked Loop and Frequency Synchronization in the Applications Information section for additional information. A graph for the voltage applied to the PLLFLTR pin vs frequency is given in Figure 2. As the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see Efficiency Considerations). The maximum switching frequency is approximately 550kHz.
2.5
PLLFLTR PIN VOLTAGE (V)
2.0
1.5
1.0
0.5
0 200
250 300 350 400 450 500 OPERATING FREQUENCY (kHz)
550
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Figure 2. Operating Frequency vs VPLLFLTR
Inductor Value Calculation and Output Ripple Current The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would
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anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because of MOSFET gate charge and transition losses. In addition to this basic tradeoff, the effect of inductor value on ripple current and low current operation must also be considered. The PolyPhase approach reduces both input and output ripple currents while optimizing individual output stages to run at a lower fundamental frequency, enhancing efficiency. The inductor value has a direct effect on ripple current. The inductor ripple current IL per individual section, N, decreases with higher inductance or frequency and increases with higher VIN or VOUT:
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IL =
VOUT VOUT 1- fL VIN
where f is the individual output stage operating frequency. In a PolyPhase converter, the net ripple current seen by the output capacitor is much smaller than the individual inductor ripple currents due to the ripple cancellation. The details on how to calculate the net output ripple current can be found in Application Note 77. Figure 3 shows the net ripple current seen by the output capacitors for the different phase configurations. The output ripple current is plotted for a fixed output voltage as the duty factor is varied between 10% and 90% on the x-axis. The output ripple current is normalized against the inductor ripple current at zero duty factor. The graph can be used in place of tedious calculations. As shown in Figure 3, the zero output ripple current is obtained when:
VOUT k = VIN N
where k = 1, 2, ..., N - 1
So the number of phases used can be selected to minimize the output ripple current and therefore the output ripple voltage at the given input and output voltages. In applications having a highly varying input voltage, additional phases will produce the best results.
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1.0 0.9 0.8 0.7 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE
IO(P-P)
0.6
VO/fL
0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN) 0.8 0.9
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Figure 3. Normalized Peak Output Current vs Duty Factor [IRMS 0.3 (IO(P-P))]
Accepting larger values of IL allows the use of low inductances, but can result in higher output voltage ripple. A reasonable starting point for setting ripple current is IL = 0.4(IOUT)/N, where N is the number of channels and IOUT is the total load current. Remember, the maximum IL occurs at the maximum input voltage. The individual inductor ripple currents are constant determined by the inductor, input and output voltages. Inductor Core Selection Once the values for L1 and L2 are known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy, or Kool M(R) cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates "hard," which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in
Kool M is a registered trademark of Magnetics, Inc.
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inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool M. Toroids are very space efficient, especially when you can use several layers of wire. Because they lack a bobbin, mounting is more difficult. However, designs for surface mount are available which do not increase the height significantly. Power MOSFET, D1 and D2 Selection Two external power MOSFETs must be selected for each controller with the LTC3729: One N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak drive levels are set by the INTVCC voltage. This voltage is typically 5V during start-up (see EXTVCC Pin Connection). Consequently, logic-level threshold MOSFETs must be used in most applications. The only exception is if low input voltage is expected (VIN < 5V); then, sublogic-level threshold MOSFETs (VGS(TH) < 3V) should be used. Pay close attention to the BVDSS specification for the MOSFETs as well; most of the logic-level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the "ON" resistance RDS(ON), reverse transfer capacitance CRSS, input voltage, and maximum output current. When the LTC3729 is operating in continuous mode the duty factors for the top and bottom MOSFETs of each output stage are given by:
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Main Switch Duty Cycle =
VOUT VIN
V -V Synchronous Switch Duty Cycle = IN OUT VIN
The MOSFET power dissipations at maximum output current are given by:
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I V PMAIN = OUT MAX 1 + RDS(ON) + VIN N 2 I k VIN MAX C RSS f N
2
()
()
(
)( )
PSYNC
I V -V = IN OUT MAX 1 + RDS(ON) VIN N
2
()
where is the temperature dependency of RDS(ON), k is a constant inversely related to the gate drive current and N is the number of stages. Both MOSFETs have I2R losses but the topside N-channel equation includes an additional term for transition losses, which peak at the highest input voltage. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actual provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. The term (1 + ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs. Temperature curve, but = 0.005/C can be used as an approximation for low voltage MOSFETs. CRSS is usually specified in the MOSFET characteristics. The constant k = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. The Schottky diodes, D1 and D2 shown in Figure 1 conduct during the dead-time between the conduction of the two large power MOSFETs. This helps prevent the body diode of the bottom MOSFET from turning on, storing charge during the dead-time, and requiring a reverse recovery period which would reduce efficiency. A 1A to 3A (depending on output current) Schottky diode is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance.
RMS INPUT RIPPLE CURRNET
DC LOAD CURRENT
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CIN and COUT Selection In continuous mode, the source current of each top N-channel MOSFET is a square wave of duty cycle VOUT/ VIN. A low ESR input capacitor sized for the maximum RMS current must be used. The details of a close form equation can be found in Application Note 77. Figure 4 shows the input capacitor ripple current for different phase configurations with the output voltage fixed and input voltage varied. The input ripple current is normalized against the DC output current. The graph can be used in place of tedious calculations. The minimum input ripple current can be achieved when the product of phase number and output voltage, N(VOUT), is approximately equal to the input voltage VIN or:
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VOUT k = VIN N
where k = 1, 2, ..., N - 1
So the phase number can be chosen to minimize the input capacitor size for the given input and output voltages. In the graph of Figure 4, the local maximum input RMS capacitor currents are reached when:
VOUT 2k - 1 = 2N VIN
0.6 0.5 0.4 0.3 0.2 0.1 0 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE
where k = 1, 2, ..., N
0.1
0.2
0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN)
0.8
0.9
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Figure 4. Normalized Input RMS Ripple Current vs Duty Factor for 1 to 6 Output Stages
These worst-case conditions are commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer's ripple current ratings are often based on only 2000 hours of life.
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This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the capacitor manufacturer if there is any question. The graph shows that the peak RMS input current is reduced linearly, inversely proportional to the number, N of stages used. It is important to note that the efficiency loss is proportional to the input RMS current squared and therefore a 2-stage implementation results in 75% less power loss when compared to a single phase design. Battery/input protection fuse resistance (if used), PC board trace and connector resistance losses are also reduced by the reduction of the input ripple current in a PolyPhase system. The required amount of input capacitance is further reduced by the factor, N, due to the effective increase in the frequency of the current pulses. The selection of COUT is driven by the required effective series resistance (ESR). Typically once the ESR requirement has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirements. The steady state output ripple (VOUT) is determined by:
1 VOUT IRIPPLE ESR + 8NfC OUT
Where f = operating frequency of each stage, N is the number of phases, COUT = output capacitance, and IRIPPLE = combined inductor ripple currents. The output ripple varies with input voltage since IL is a function of input voltage. The output ripple will be less than 50mV at max VIN with IL = 0.4IOUT(MAX)/N assuming: COUT required ESR < 2N(RSENSE) and COUT > 1/(8Nf)(RSENSE) The emergence of very low ESR capacitors in small, surface mount packages makes very physically small implementations possible. The ability to externally compensate the switching regulator loop using the ITH pin(OPTI-LOOP compensation) allows a much wider selection of output capacitor types. OPTI-LOOP compensation effectively removes constraints on output capacitor
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ESR. The impedance characteristics of each capacitor type are significantly different than an ideal capacitor and therefore require accurate modeling or bench evaluation during design. Manufacturers such as Nichicon, United Chemicon and Sanyo should be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo and the Panasonic SP surface mount types have the lowest (ESR)(size) product of any aluminum electrolytic at a somewhat higher price. An additional ceramic capacitor in parallel with OS-CON type capacitors is recommended to reduce the inductance effects. In surface mount applications, multiple capacitors may have to be paralleled to meet the ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. New special polymer surface mount capacitors offer very low ESR also but have much lower capacitive density per unit volume. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. Several excellent choices are the AVX TPS, AVX TPSV or the KEMET T510 series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. Other capacitor types include Sanyo OS-CON, Nichicon PL series and Sprague 595D series. Consult the manufacturer for other specific recommendations. A combination of capacitors will often result in maximizing performance and minimizing overall cost and size. INTVCC Regulator An internal P-channel low dropout regulator produces 5V at the INTVCC pin from the VIN supply pin. The INTVCC regulator powers the drivers and internal circuitry of the LTC3729. The INTVCC pin regulator can supply up to 50mA peak and must be bypassed to power ground with a minimum of 4.7F tantalum or electrolytic capacitor. An additional 1F ceramic capacitor placed very close to the IC is recommended due to the extremely high instantaneous currents required by the MOSFET gate drivers. High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the
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maximum junction temperature rating for the LTC3729 to be exceeded. The supply current is dominated by the gate charge supply current, in addition to the current drawn from the differential amplifier output. The gate charge is dependent on operating frequency as discussed in the Efficiency Considerations section. The supply current can either be supplied by the internal 5V regulator or via the EXTVCC pin. When the voltage applied to the EXTVCC pin is less than 4.7V, all of the INTVCC load current is supplied by the internal 5V linear regulator. Power dissipation for the IC is higher in this case by (IIN)(VIN - INTVCC) and efficiency is lowered. The junction temperature can be estimated by using the equations given in Note 1 of the Electrical Characteristics. For example, the LTC3729 VIN current is limited to less than 24mA from a 24V supply: TJ = 70C + (24mA)(24V)(95C/W) = 125C Use of the EXTVCC pin reduces the junction temperature to: TJ = 70C + (24mA)(5V)(95C/W) = 81.4C The input supply current should be measured while the controller is operating in continuous mode at maximum VIN and the power dissipation calculated in order to prevent the maximum junction temperature from being exceeded. EXTVCC Connection The LTC3729 contains an internal P-channel MOSFET switch connected between the EXTVCC and INTVCC pins. When the voltage applied to EXTVCC rises above 4.7V, the internal regulator is turned off and the switch closes, connecting the EXTVCC pin to the INTVCC pin thereby supplying internal and MOSFET gate driving power. The switch remains closed as long as the voltage applied to EXTVCC remains above 4.5V. This allows the MOSFET driver and control power to be derived from the output during normal operation (4.7V < VEXTVCC < 7V) and from the internal regulator when the output is out of regulation (start-up, short-circuit). Do not apply greater than 7V to the EXTVCC pin and ensure that EXTVCC < VIN + 0.3V when using the application circuits shown. If an external voltage source is applied to the EXTVCC pin when the VIN supply is not present, a diode can be placed in series with the LTC3729's VIN pin and a Schottky diode between the
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EXTVCC and the VIN pin, to prevent current from backfeeding VIN. Significant efficiency gains can be realized by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be scaled by the ratio: (Duty Factor)/(Efficiency). For 5V regulators this means connecting the EXTVCC pin directly to VOUT. However, for 3.3V and other lower voltage regulators, additional circuitry is required to derive INTVCC power from the output. The following list summarizes the four possible connections for EXTVCC: 1. EXTVCC left open (or grounded). This will cause INTVCC to be powered from the internal 5V regulator resulting in a significant efficiency penalty at high input voltages. 2. EXTVCC connected directly to VOUT. This is the normal connection for a 5V regulator and provides the highest efficiency. 3. EXTVCC connected to an external supply. If an external supply is available in the 5V to 7V range, it may be used to power EXTVCC providing it is compatible with the MOSFET gate drive requirements. VIN must be greater than or equal to the voltage applied to the EXTVCC pin. 4. EXTVCC connected to an output-derived boost network. For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXTVCC to an outputderived voltage which has been boosted to greater than 4.7V but less than 7V. This can be done with either the inductive boost winding as shown in Figure 5a or the capacitive charge pump shown in Figure 5b. The charge pump has the advantage of simple magnetics. Topside MOSFET Driver Supply (CB,DB) (Refer to Functional Diagram) External bootstrap capacitors CB1 and CB2 connected to the BOOST1 and BOOST2 pins supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the Functional Diagram is charged though diode DB from INTVCC when the SW pin is low. When the topside MOSFET turns on, the driver places the CB voltage across the gate-source of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node
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OPTIONAL EXTVCC CONNECTION 5V < VSEC < 7V + CIN LTC3729 VIN TG1 EXTVCC SW1 N-CH 6.8V RSENSE T1 VIN
1N4148
VSEC
+
1F
EXTVCC
+
BG1 N-CH PGND
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Figure 5a. Secondary Output Loop and EXTVCC Connection
voltage, SW, rises to VIN and the BOOST pin rises to VIN + VINTVCC. The value of the boost capacitor CB needs to be 30 to 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of DB must be greater than VIN(MAX). The final arbiter when defining the best gate drive amplitude level will be the input supply current. If a change is made that decreases input current, the efficiency has improved. If the input current does not change then the efficiency has not changed either. Differential Amplifier/Output Voltage The LTC3729 has a true remote voltage sense capablity. The sensing connections should be returned from the load back to the differential amplifier's inputs through a common, tightly coupled pair of PC traces. The differential amplifier rejects common mode signals capacitively or inductively radiated into the feedback PC traces as well as ground loop disturbances. The differential amplifier output signal is divided down and compared with the internal precision 0.8V voltage reference by the error amplifier. The differential amplifier utilizes a set of internal precision resistors to enable precision instrumentation-type measurement of the output voltage. The output is an NPN emitter follower without any internal pull-down current. A DC resistive load to ground is required in order to sink current. The output will swing from 0V to 10V. (VIN VDIFFOUT + 2V.) The output voltage is set by an external resistive divider according to the following formula:
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CIN LTC3729 VIN TG1 N-CH VN2222LL RSENSE SW1 L1 VOUT BAT85 BAT85 0.22F VIN
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1F
BAT85
VOUT COUT
+
BG1 N-CH PGND
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COUT
Figure 5b. Capacitive Charge Pump for EXTVCC
R2 VOUT = 0.8 V 1 + R1 where R1 and R2 are defined in Figure 2. Soft-Start/Run Function The RUN/SS pin provides three functions: 1) Run/Shutdown, 2) soft-start and 3) a defeatable short-circuit latchoff timer. Soft-start reduces the input power sources' surge currents by gradually increasing the controller's current limit ITH(MAX). The latchoff timer prevents very short, extreme load transients from tripping the overcurrent latch. A small pull-up current (>5A) supplied to the RUN/ SS pin will prevent the overcurrent latch from operating. The following explanation describes how the functions operate. An internal 1.2A current source charges up the CSS capacitor. When the voltage on RUN/SS reaches 1.5V, the controller is permitted to start operating. As the voltage on RUN/SS increases from 1.5V to 3.0V, the internal current limit is increased from 25mV/RSENSE to 75mV/RSENSE. The output current limit ramps up slowly, taking an additional 1.4s/F to reach full current. The output current thus ramps up slowly, reducing the starting surge current required from the input power supply. If RUN/SS has been pulled all the way to ground there is a delay before starting of approximately:
tDELAY =
1.5V C SS = 1.25s / F C SS 1.2A
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tRAMP = 3V - 1.5V C SS = 1.25s / F C SS 1.2A
The time for the output current to ramp up is then:
(
)
By pulling the RUN/SS pin below 0.8V the LTC3729 is put into low current shutdown (IQ < 40A). RUN/SS can be driven directly from logic as shown in Figure 6. Diode D1 in Figure 6 reduces the start delay but allows CSS to ramp up slowly providing the soft-start function. The RUN/SS pin has an internal 6V zener clamp (see Functional Diagram). Fault Conditions: Overcurrent Latchoff The RUN/SS pin also provides the ability to latch off the controllers when an overcurrent condition is detected. The RUN/SS capacitor, CSS, is used initially to limit the inrush current of both controllers. After the controllers have been started and been given adequate time to charge up the output capacitors and provide full load current, the RUN/ SS capacitor is used for a short-circuit timer. If the output voltage falls to less than 70% of its nominal value after CSS reaches 4.1V, CSS begins discharging on the assumption that the output is in an overcurrent condition. If the condition lasts for a long enough period as determined by the size of CSS, the controller will be shut down until the RUN/SS pin voltage is recycled. If the overload occurs during start-up, the time can be approximated by: tLO1 (CSS * 0.6V)/(1.2A) = 5 * 105 (CSS) If the overload occurs after start-up, the voltage on CSS will continue charging and will provide additional time before latching off: tLO2 (CSS * 3V)/(1.2A) = 2.5 * 106 (CSS) This built-in overcurrent latchoff can be overridden by providing a pull-up resistor, RSS, to the RUN/SS pin as shown in Figure 6. This resistance shortens the soft-start period and prevents the discharge of the RUN/SS capacitor during a severe overcurrent and/or short-circuit condition. When deriving the 5A current from VIN as in the figure, current latchoff is always defeated. Diodeconnecting this pull-up resistor to INTVCC, as in Figure 6, eliminates any extra supply current during shutdown
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VIN 3.3V OR 5V D1 RUN/SS RSS* D1* CSS CSS INTVCC RSS* RUN/SS *OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF
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Figure 6. RUN/SS Pin Interfacing
while eliminating the INTVCC loading from preventing controller start-up. Why should you defeat current latchoff? During the prototyping stage of a design, there may be a problem with noise pickup or poor layout causing the protection circuit to latch off the controller. Defeating this feature allows troubleshooting of the circuit and PC layout. The internal short-circuit and foldback current limiting still remains active, thereby protecting the power supply system from failure. A decision can be made after the design is complete whether to rely solely on foldback current limiting or to enable the latchoff feature by removing the pull-up resistor. The value of the soft-start capacitor CSS may need to be scaled with output voltage, output capacitance and load current characteristics. The minimum soft-start capacitance is given by: CSS > (COUT )(VOUT)(10-4)(RSENSE) The minimum recommended soft-start capacitor of CSS = 0.1F will be sufficient for most applications. Phase-Locked Loop and Frequency Synchronization The LTC3729 has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector. This allows the top MOSFET turn-on to be locked to the rising edge of an external source. The frequency range of the voltage controlled oscillator is 50% around the center frequency fO. A voltage applied to the PLLFLTR pin of 1.2V corresponds to a frequency of approximately 400kHz. The nominal operating frequency range of the LTC3729 is 250kHz to 550kHz.
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The phase detector used is an edge sensitive digital type which provides zero degrees phase shift between the external and internal oscillators. This type of phase detector will not lock up on input frequencies close to the harmonics of the VCO center frequency. The PLL hold-in range, fH, is equal to the capture range, fC: fH = fC = 0.5 fO (250kHz-550kHz) The output of the phase detector is a complementary pair of current sources charging or discharging the external filter network on the PLLFLTR pin. A simplified block diagram is shown in Figure 7.
2.4V RLP 10k CLP
PHASE DETECTOR
EXTERNAL OSC
PLLFLTR PLLIN
50k
DIGITAL PHASE/ FREQUENCY DETECTOR
OSC
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Figure 7. Phase-Locked Loop Block Diagram
If the external frequency (fPLLIN) is greater than the oscillator frequency f0SC, current is sourced continuously, pulling up the PLLFLTR pin. When the external frequency is less than f0SC, current is sunk continuously, pulling down the PLLFLTR pin. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. Thus the voltage on the PLLFLTR pin is adjusted until the phase and frequency of the external and internal oscillators are identical. At this stable operating point the phase comparator output is open and the filter capacitor CLP holds the voltage. The LTC3729 PLLIN pin must be driven from a low impedance source such as a logic gate located close to the pin. When using multiple LTC3729's for a phase-locked system, the PLLFLTR pin of the master oscillator should be biased at a voltage that will guarantee the slave oscillator(s) ability
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to lock onto the master's frequency. A DC voltage of 0.7V to 1.7V applied to the master oscillator's PLLFLTR pin is recommended in order to meet this requirement. The resultant operating frequency will be approximately 500kHz. The loop filter components (CLP, RLP) smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP =10k and CLP is 0.01F to 0.1F. Minimum On-Time Considerations Minimum on-time tON(MIN) is the smallest time duration that the LTC3729 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that:
tON(MIN) < VOUT VIN f
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If the duty cycle falls below what can be accommodated by the minimum on-time, the LTC3729 will begin to skip cycles resulting in nonconstant frequency operation. The output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. The minimum on-time for the LTC3729 is approximately 100ns. However, as the peak sense voltage decreases the minimum on-time gradually increases. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. If an application can operate close to the minimum ontime limit, an inductor must be chosen that has a low enough inductance to provide sufficient ripple amplitude to meet the minimum on-time requirement. As a general rule, keep the inductor ripple current of each phase equal to or greater than 15% of IOUT(MAX)/N at VIN(MAX).
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Voltage Positioning
Voltage positioning can be used to minimize peak-to-peak output voltage excursions under worst-case transient loading conditions. The open-loop DC gain of the control loop is reduced depending upon the maximum load step specifications. Voltage positioning can easily be added to the LTC3729 by loading the ITH pin with a resistive divider having a Thevenin equivalent voltage source equal to the midpoint operating voltage range of the error amplifier, or 1.2V (see Figure 8).
INTVCC RT2 ITH RT1 RC CC
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LTC3729
Figure 8. Active Voltage Positioning Applied to the LTC3729
The resistive load reduces the DC loop gain while maintaining the linear control range of the error amplifier. The maximum output voltage deviation can theoretically be reduced to half or alternatively the amount of output capacitance can be reduced for a particular application. A complete explanation is included in Design Solutions 10. (See www.linear-tech.com) Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3729 circuits: 1) LTC3729 VIN current (including loading on the differential amplifier output),
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2) INTVCC regulator current, 3) I2R losses and 4) Topside MOSFET transition losses. 1) The VIN current has two components: the first is the DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control currents; the second is the current drawn from the differential amplifier output. VIN current typically results in a small (<0.1%) loss. 2) INTVCC current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from INTVCC to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the control circuit current. In continuous mode, IGATECHG = (QT + QB), where QT and QB are the gate charges of the topside and bottom side MOSFETs. Supplying INTVCC power through the EXTVCC switch input from an output-derived source will scale the VIN current required for the driver and control circuits by the ratio (Duty Factor)/(Efficiency). For example, in a 20V to 5V application, 10mA of INTVCC current results in approximately 3mA of VIN current. This reduces the mid-current loss from 10% or more (if the driver was powered directly from VIN) to only a few percent. 3) I2R losses are predicted from the DC resistances of the fuse (if used), MOSFET, inductor, current sense resistor, and input and output capacitor ESR. In continuous mode the average output current flows through L and RSENSE, but is "chopped" between the topside MOSFET and the synchronous MOSFET. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L, RSENSE and ESR to obtain I2R losses. For example, if each RDS(ON)=10m, RL=10m, and RSENSE=5m, then the total resistance is 25m. This results in losses ranging from 2% to 8% as the output current increases from 3A to 15A per output stage for a 5V output, or a 3% to 12% loss per output stage for a 3.3V output. Efficiency varies as the inverse square of VOUT for the same external components and output power level. The combined effects of
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LTC3729
APPLICATIO S I FOR ATIO
increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4) Transition losses apply only to the topside MOSFET(s), and only when operating at high input voltages (typically 20V or greater). Transition losses can be estimated from: Transition Loss = (1.7) VIN2 IO(MAX) CRSS f Other "hidden" losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. It is very important to include these "system" level losses in the design of a system. The internal battery and input fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and a very low ESR at the switching frequency. A 50W supply will typically require a minimum of 200F to 300F of capacitance having a maximum of 10m to 20m of ESR. The LTC3729 PolyPhase architecture typically halves to quarters this input capacitance requirement over competing solutions. Other losses including Schottky conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ILOAD(ESR), where ESR is the effective series resistance of COUT(ILOAD) also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the ITH pin not only allows optimization of control loop behavior but also provides a DC coupled and AC filtered closed loop response test point. The DC step, rise time, and settling at this test point truly reflects the closed loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be
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estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Figure 1 circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.2 to 5 times their suggested values) to maximize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be decided upon because the various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of <2s will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the Ith pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. A second, more severe transient is caused by switching in loads with large (>1F) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 * CLOAD. Thus a 10F capacitor would require a 250s rise time, limiting the charging current to about 200mA.
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LTC3729
APPLICATIO S I FOR ATIO
Design Example (Using Two Phases)
As a design example, assume VIN = 5V (nominal), VIN = 5.5V (max), VOUT = 1.8V, IMAX = 20A, TA = 70C and f = 300kHz. The inductance value is chosen first based on a 30% ripple current assumption. The highest value of ripple current occurs at the maximum input voltage. Tie the PLLFLTR pin to a resistive divider using the INTVCC pin to generate 1V for 300kHz operation. The minimum inductance for 30% ripple current is:
L
VOUT VOUT 1- VIN f I
1.8V 1.8V 1- 300kHz 30% 10A 5.5V 1.35H
()
(
)( )( )
A 2H inductor will produce 20% ripple current. The peak inductor current will be the maximum DC value plus one half the ripple current, or 11.5A. The minimum on-time occurs at maximum VIN:
tON(MIN) = VOUT 1.8V = = 1.1s VINf 5.5V 300kHz
( )(
)
The RSENSE resistors value can be calculated by using the maximum current sense voltage specification with some accomodation for tolerances: RSENSE = 50mV 0.005 11.5A
Choosing 1% resistors: R1 = 16.5k and R2 = 13.2k yields an output voltage of 1.80V.
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The power dissipation on the topside MOSFET can be easily estimated. Using a Siliconix Si4420DY for example; RDS(ON) = 0.013, CRSS = 300pF. At maximum input voltage with Tj (estimated) = 110C at an elevated ambient temperature: PMAIN =
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( ) [ ( )( )] 2 0.013 + 1.7(5.5V ) (10A )(300pF ) (310kHz)= 0.61W
2 1.8V 10 1 + 0.005 110C - 25C 5.5V
The worst-case power disipated by the synchronous MOSFET under normal operating conditions at elevated ambient temperature and estimated 50C junction temperature rise is:
PSYNC =
5.5V - 1.8V 10A 5.5V = 1.29W
( ) (1.48)(0.013)
2
A short-circuit to ground will result in a folded back current of:
ISC
25mV 1 200ns 5.5V = + 0.005 2 2H
( ) = 5.28A

The worst-case power disipated by the synchronous MOSFET under short-circuit conditions at elevated ambient temperature and estimated 50C junction temperature rise is:
PSYNC =
5.5V - 1.8V 5.28A 5.5V = 360mW
(
) (1.48)(0.013)
2
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LTC3729
APPLICATIO S I FOR ATIO
which is much less than normal, full-load conditions. Incidentally, since the load no longer dissipates power in the shorted condition, total system power dissipation is decreased by over 99%. The duty cycles when the peak RMS input current occurs is at D = 0.25 and D = 0.75 according to Figure 4. Calculate the worst-case required RMS input current rating at the input voltage, which is 5.5V, that provides a duty cycle nearest to the peak. From Figure 4, CIN will require an RMS current rating of:
CIN required IRMS = 20A 0.23 = 4.6ARMS
( )( )
The output capacitor ripple current is calculated by using the inductor ripple already calculated for each inductor and multiplying by the factor obtained from Figure 3 along with the calculated duty factor. The output ripple in continuous mode will be highest at the maximum input voltage. From Figure 3, the maximum output current ripple is:
VOUT 0.34 fL 1.8 0.34 ICOUTMAX = = 1A 300kHz 2H ICOUT =
Note that the PolyPhase technique will have its maximum benefit for input and output ripple currents when the number of phases times the output voltage is approximately equal to or greater than the input voltage. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3729. These items are also illustrated graphically in the layout diagram of Figure 11. Check the following in your layout:
() () ( )( )
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1) Are the signal and power grounds segregated? The LTC3729 signal ground pin should return to the (-) plate of COUT separately. The power ground returns to the sources of the bottom N-channel MOSFETs, anodes of the Schottky diodes, and (-) plates of CIN, which should have as short lead lengths as possible. 2) Does the LTC3729 VOS+ pin connect to the (+) plate(s) of COUT? Does the LTC3729 VOS- pin connect to the (-) plate(s) of COUT? The resistive divider R1, R2 must be connected between the VDIFFOUT and signal ground and any feedforward capacitor across R1 should be as close as possible to the LTC3729. 3) Are the SENSE - and SENSE + leads routed together with minimum PC trace spacing? The filter capacitors between SENSE + and SENSE - pin pairs should be as close as possible to the LTC3729. Ensure accurate current sensing with Kelvin connections to the sense resistors. 4) Do the (+) plates of CIN connect to the drains of the topside MOSFETs as closely as possible? This capacitor provides the AC current to the MOSFETs. Keep the input current path formed by the input capacitor, top and bottom MOSFETs, and the Schottky diode on the same side of the PC board in a tight loop to minimize conducted and radiated EMI. 5) Is the INTVCC 1F ceramic decoupling capacitor connected closely between INTVCC and the power ground pin? This capacitor carries the MOSFET driver peak currents. A small value is used to allow placement immediately adjacent to the IC. 6) Keep the switching nodes, SW1 (SW2), away from sensitive small-signal nodes. Ideally the switch nodes should be placed at the furthest point from the LTC3729. 7) Use a low impedance source such as a logic gate to drive the PLLIN pin and keep the lead as short as possible. 8) Minimize the capacitive load on the CLKOUT pin to minimize excess phase shift. Buffer if necessary with an NPN emitter follower.
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APPLICATIO S I FOR ATIO
The diagram in Figure 9 illustrates all branch currents in a 2-phase switching regulator. It becomes very clear after studying the current waveforms why it is critical to keep the high-switching-current paths to a small physical size. High electric and magnetic fields will radiate from these "loops" just as radio stations transmit signals. The output capacitor ground should return to the negative terminal of the input capacitor and not share a common ground path with any switched current paths. The left half of the circuit gives rise to the "noise" generated by a switching regulator. The ground terminations of the sychronous MOSFETs and Schottky diodes should return to the
SW1
D1
VIN RIN CIN
+
SW2
D2 BOLD LINES INDICATE HIGH, SWITCHING CURRENT LINES. KEEP LINES TO A MINIMUM LENGTH.
3729 F09
Figure 9. Instantaneous Current Path Flow in a Multiple Phase Switching Regulator
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bottom plate(s) of the input capacitor(s) with a short isolated PC trace since very high switched currents are present. A separate isolated path from the bottom plate(s) of the input capacitor(s) should be used to tie in the IC power ground pin (PGND) and the signal ground pin (SGND). This technique keeps inherent signals generated by high current pulses from taking alternate current paths that have finite impedances during the total period of the switching regulator. External OPTI-LOOP compensation allows overcompensation for PC layouts which are not optimized but this is not the recommended design procedure.
L1 RSENSE1 VOUT COUT RL
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L2
RSENSE2
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APPLICATIO S I FOR ATIO
Simplified Visual Explanation of How a 2-Phase Controller Reduces Both Input and Output RMS Ripple Current A multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is divided by, and the effective ripple frequency is multiplied up by the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by, and the effective ripple frequency is increased by the number of phases used. Figure 10 graphically illustrates the principle.
SINGLE PHASE SW V
ICIN
ICOUT DUAL PHASE SW1 V SW2 V
IL1
IL2 ICIN ICOUT RIPPLE
3729 F10
Figure 10. Single and PolyPhase Current Waveforms
The worst-case RMS ripple current for a single stage design peaks at twice the value of the output voltage . The worst-case RMS ripple current for a two stage design results in peaks at 1/4 and 3/4 of input voltage. When the RMS current is calculated, higher effective duty factor results and the peak current levels are divided as long as the currents in each stage are balanced. Refer to Application Note 19 for a detailed description of how to calculate RMS current for the single stage switching regulator. Figures 3 and 4 help to illustrate how the input and output
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currents are reduced by using an additional phase. The input current peaks drop in half and the frequency is doubled for a 2-phase converter. The input capacity requirement is reduced theoretically by a factor of four! A ceramic input capacitor with its unbeatably low ESR characteristic can be used. Figure 4 illustrates the RMS input current drawn from the input capacitance versus the duty cycle as determined by the ratio of input and output voltage. The peak input RMS current level of the single phase system is reduced by 50% in a 2-phase solution due to the current splitting between the two stages. An interesting result of the multi-phase solution is that the VIN which produces worst-case ripple current for the input capacitor, VOUT = VIN/2, in the single phase design produces zero input current ripple in the 2-phase design. The output ripple current is reduced significantly when compared to the single phase solution using the same inductance value because the VOUT/L discharge current term from the stage(s) that has its bottom MOSFET on subtracts current from the (VIN - VOUT)/L charging current resulting from the stage which has its top MOSFET on. The output ripple current is:
IRIPPLE = 2VOUT fL 1 - 2D (1 - D) 1 - 2D + 1
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where D is duty factor. The input and output ripple frequency is increased by the number of stages used, reducing the output capacity requirements. When VIN is approximately equal to NVOUT as illustrated in Figures 3 and 4, very low input and output ripple currents result. Again, the interesting result of 2-phase operation results in no output ripple at VOUT = VIN/2. The addition of more phases by phase locking additional controllers always results in no net input or output ripple at VOUT/VIN ratios equal to the number of stages implemented. Designing a system with a multiple of stages close to the VOUT/VIN ratio will significantly reduce the ripple voltage at the input and outputs and thereby improve efficiency, physical size, and heat generation of the overall switching power supply.
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LTC3729
TYPICAL APPLICATIO S
OPTIONAL SYNC CLOCK IN 0.33F 8.06k, 1% L1 1000pF 1 2 3 4 5 0.33F 6800pF 100pF 25.5k, 1% 470pF 6 7 8 9 10 11 12 13 14 1000pF 24k 75k RUN/SS SENSE1 + SENSE1 - EAIN PLLFLTR PLLIN LTC3729 PHASMD ITH SGND VDIFFOUT VOS - VOS + SENSE2 - SENSE2 + CLKOUT TG1 SW1 BOOST1 VIN BG1 EXTVCC INTVCC PGND BG2 BOOST2 SW2 TG2 PGOOD 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0.47F M4 L2 M5 M6 D8 D2 MBRS 340T3 5V 1F,6.3V 0.47F D7 10 1F M1 M2 M3 0.003
47k
+
+
1000pF
1 2 3
47pF 10k 0.01F 1nF
4 5 6 7
8 I 100pF 9 TH SGND 10 NC V 11 DIFFOUT V- 12 OS + V 13 OS SENSE2 - 14 SENSE2 + 1000pF
+
PGND BG2 BOOST2 SW2 TG2 PGOOD
20 19 18 17 16 15 0.47F D10
+
1000pF
1 2 3
47pF 10k 0.01F 1nF
4 5 6 7
8 I 100pF 9 TH SGND 10 NC V 11 DIFFOUT V- 12 OS + V 13 OS SENSE2 - 14 SENSE2 + 1000pF
+
PGND BG2 BOOST2 SW2 TG2 PGOOD
19 18 17 16 15 0.47F M16 L6 M17 M18 D12 D6 MBRS 340T3
+
VIN: 12V VOUT: 3.3V/90A SWITCHING FREQUENCY = 400kHz
MI - M18: Si7440DP L1 - L6: 1H PANASONIC ETQP6F1R0S D7 - D12: CENTROL CMDSH-3TR
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D1 MBRS 340T3
+
22F 6.3V
2X150F 16V
GND
3X330F, 6.3V POSCAP VOUT 3.3V/90A
0.003
L3 RUN/SS SENSE1 + SENSE1 - EAIN PLLFLTR PLLIN LTC3729 PHASMD CLKOUT TG1 SW1 BOOST1 VIN BG1 EXTVCC INTVCC 28 27 26 25 24 23 22 21 5V 1F,6.3V 0.47F D9 10 1F 22F 6.3V 2X150F 16V GND M7 M8 M9
0.003
D3 MBRS 340T3 3X330F, 6.3V
POSCAP
M10 L4
M11
M12
D4 MBRS 340T3
+
VIN 12V 0.003
L5 RUN/SS SENSE1 + SENSE1 - EAIN PLLFLTR PLLIN LTC3729 PHASMD CLKOUT TG1 SW1 BOOST1 VIN BG1 EXTVCC INTVCC 28 27 26 25 24 23 22 21 20 5V 1F,6.3V 0.47F D11 10 1F 22F 6.3V 2X150F 16V GND M13 M14 M15
0.003
D5 MBRS 340T3 3X330F, 6.3V
POSCAP
+
0.003
OUTPUT CAPACITORS: SANYO 6TPB330M
3729 TA03
Figure 11. High Current 3.3V/90A 6-Phase Application
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LTC3729
PACKAGE DESCRIPTIO
5.20 - 5.38** (0.205 - 0.212)
0 - 8 7.65 - 7.90 (0.301 - 0.311) 0.05 - 0.21 (0.002 - 0.008)
0.13 - 0.22 (0.005 - 0.009)
0.55 - 0.95 (0.022 - 0.037)
0.65 (0.0256) BSC
NOTE: DIMENSIONS ARE IN MILLIMETERS *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
5.35 0.05 4.20 0.05 3.45 0.05 (4 SIDES)
RECOMMENDED SOLDER PAD LAYOUT 5.00 0.10 (4 SIDES) 0.75 0.05 0.00 - 0.05
PIN 1 TOP MARK
NOTE: 1. DRAWING PROPOSED TO INCLUDE JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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(For purposes of clarity, drawings are not to scale) G Package 28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
10.07 - 10.33* (0.397 - 0.407) 1.73 - 1.99 (0.068 - 0.078) 28 27 26 25 24 23 22 21 20 19 18 17 16 15
0.25 - 0.38 (0.010 - 0.015)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
G28 SSOP 1098
UH Package 32-Lead Plastic QFN (5mm x 5mm)
(Reference LTC DWG # 05-08-1693)
0.57 0.05
PACKAGE OUTLINE 0.23 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP 31 32 0.40 0.10
1 2
3.45 0.10 (4-SIDES)
(UH) QFN 0102
0.200 REF
0.23 0.05 0.50 BSC
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LTC3729
TYPICAL APPLICATIO
1000pF 0.1F 1 2 3 4 13.2k 1000pF 5 6 7 8 9 16.5k 10 11 12 100pF 13 14 1000pF 3.3k 33pF
+
SGND VDIFFOUT VOS - VOS
+
LTC3729
PGND BG2 BOOST2 SW2 TG2 PGOOD
20 19 18 17 16 15 D4 100k
+
VIN: 5V TO 16V VOUT: 3.3V/30A SWITCHING FREQUENCY = 250kHz
MI, M3: IRF7811 M2, M4: IRF7809 L1, L2: 1H SUMIDA CEP125-1R0MC-H
Figure 12. 3.3V/30A Power Supply with Active Voltage Positioning
RELATED PARTS
PART NUMBER LTC1436A-PLL LTC1438/LTC1439 LTC1438-ADJ LTC1530 LTC1538-AUX/ LTC1539 DESCRIPTION Low Noise Synchronous Step-Down Switching Regulator Dual Low Noise Synchronous Step-Down Switching Regulators Dual Synchronous Controller with Auxiliary Regulator High Power Step-Down Switching Regulator Controller Dual Low Noise Synchronous Step-Down Switching Regulators COMMENTS Adaptive PowerTM Mode, 24-Pin SSOP POR, Auxiliary Regulator POR, External Feedback Divider High Efficiency 5V to 3.3V Conversion at Up to 15A 5V Standby, POR, Low-Battery, Aux Regulator Constant Frequency, Standby, 5V and 3.3V LDOs, Power Good 500kHz, 25MHz GBW, Voltage Mode Constant Frequency, 5-Bit VID, Standby 5V, 3.3V, Power Good Current Mode Ensures Accurate Current Sharing, 3.5V VIN 36V Burst Mode(R) Operation, 16-Pin Narrow SSOP, Fault Protection, 3.5V VIN 36V Output Fault Protection, Power Good, 24-Pin SSOP, 3.5V VIN 36V Up to 97% Efficiency, 4V V2V 36V, 0.8V VOUT (0.9)(VIN), IOUT up to 20A Low Cost, 2-Phase Current Mode Synchronizable, Current Mode, 3.5V VIN 36V SSOP and QFN Packages
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LTC1628/LTC1628-PG 2-Phase, Dual Output Synchronous Step-Down DC/DC Controller LTC1828-SYNC LTC1702/LTC1703 LTC1708-PG Dual PolyPhase Synchronous Step-Down Switching Regulator Dual PolyPhase Synchronous Step-Down Switching Regulator
LTC1709/LTC1709-7 2-Phase Synchronous Step-Down Switching Regulators with 5-Bit VID LTC1709-8/LTC1709-9 LTC1735 LTC1736 LTC1778 Synchronous Step-Down Controller Synchronous Step-Down Controller with 5-Bit VID No RSENSE Current Mode Synchronous Step-Down Controller
LTC1929/LTC1929-PG 2-Phase Synchronous Controllers LTC3728 550kHz, 2-Phase Dual Output Synchronous Step-Down Controller
Burst Mode is a registered trademark of Linear Technology Corporation. Adaptive Power is a trademark of Linear Technology Corporation.
28 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507 q www.linear.com
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L1 RUN/SS SENSE1 + SENSE1 EAIN PLLFLTR PLLIN PHASMD ITH
-
0.003
CLKOUT TG1 SW1 BOOST1 VIN BG1 EXTVCC INTVCC
28 27 26 25 24 23 22 21 5V 1F,6.3V D3 10 0.1F CIN 4.7F 6.3V 0.47F M1 M2
D1 UPS840
COUT
SENSE2 - SENSE2 +
0.47F
POWER GOOD
D2 UPS840 M3 L2 M4 VOUT 3.3V/30A
+
VIN 5V TO 16V 0.003
CIN: OS CON 2-16SP270M COUT: KEMET 3-T510 470F D3, D4: CENTRAL CMDSH-3TR
3729TA02
LT/CPI 0302 1.5K REV A * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 2001

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